`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    00:53:29 05/19/2013 
// Design Name: 
// Module Name:    IRQDecoder 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module IRQDecoder(
    input enable,
    input [3:0] IRQNumber,
    output [15:0] enableWires
    );
	 reg [15:0] enableWiresReg;
	 assign enableWires = enableWiresReg;
	 always @(*) begin
		if(enable) begin
			case(IRQNumber)
				4'd0:  enableWiresReg = 16'b0000000000000001;
				4'd1:  enableWiresReg = 16'b0000000000000010;
				4'd2:  enableWiresReg = 16'b0000000000000100;
				4'd3:  enableWiresReg = 16'b0000000000001000;
				4'd4:  enableWiresReg = 16'b0000000000010000;
				4'd5:  enableWiresReg = 16'b0000000000100000;
				4'd6:  enableWiresReg = 16'b0000000001000000;
				4'd7:  enableWiresReg = 16'b0000000010000000;
				4'd8:  enableWiresReg = 16'b0000000100000000;
				4'd9:  enableWiresReg = 16'b0000001000000000;
				4'd10: enableWiresReg = 16'b0000010000000000;
				4'd11: enableWiresReg = 16'b0000100000000000;
				4'd12: enableWiresReg = 16'b0001000000000000;
				4'd13: enableWiresReg = 16'b0010000000000000;
				4'd14: enableWiresReg = 16'b0100000000000000;
				4'd15: enableWiresReg = 16'b1000000000000000;
			endcase
		end
		else  enableWiresReg = 16'b0;
	 end


endmodule
